Research Scientist with a focus on memory management architectures for security.
MS, PhD, and Postdoc in Computer Science, 2012
University of Illinois at Urbana-Champaign
BS in Computer Science, 2005
University of Wisconsin-Eau Claire
Advisor: Carl A. Gunter
National Defense Science and Engineering Graduate (NDSEG) Fellow
PhD Dissertation: Compact Integrity-Aware Architectures
MS Thesis: Dependable Emergency-Response Networking Based on Retaskable Network Infrastructures
TA for Advanced Computer Security (Instructor: Carl A. Gunter)
TA for Advanced Operating Systems (Instructor: Samuel T. King)
Touchless dispensing with a photoresistor sensor and a PWM-controlled servo
Configuring bounds registers and extending LLVM and Clang to instrument code to help prevent corruption of the safe stacks.
Based on Contiki OS with the lightweight X86 protection domain support that I implemented.
Unofficial driver for the X10 CM19A remote control interface in Python, now maintained by Burns Fisher.
Memory management based on paging, software-switched segments, or hardware task switching.
We developed a Network-on-Chip (NoC) firewall in Bluespec SystemVerilog configured by a dedicated core, and we demonstrated how it can enforce isolation between two instances of Linux on separate cores. We developed a shallow embedding of a subset of Bluespec into Maude, since both languages are based on term rewriting systems, and we used a Maude model of the NoC firewall to precisely identify a subtle vulnerability.
Extended a processor core written in VHDL with hardware support for detecting attempts to execute unverified code. Developed an integrity kernel and network server to enforce code whitelisting using processor extensions. Evaluated using an FPGA.
Price-responsive electrical demand-response system, e.g. for laptops and air conditioners, with multiple loci of control.
Issued patents:
Published patent applications:
App, kernel, and hypervisor development for Linux, Windows, and embedded systems with Boost and generics experience
Somewhat familar with assembly language for other architectures as well
Compiler framework
High-Level Synthesis (HLS) language based on Term-Rewriting Systems
Model checker based on Term-Rewriting Systems and Linear-Temporal Logic
Interactive theorem prover
Experience using Intel Quartus and Xilinx Vivado FPGA toolchains. Experience using Synopsys VCS and Mentor Graphics Modelsim simulators. Experience extending and maintaining an in-house Verilog simulator during an internship with Cray, Inc.
Logic programming language
Professional society memberships:
PC member:
Journal reviews:
Conference and workshop reviews:
Volunteering:
