Michael LeMay

Research Scientist

Intel Labs


Research Scientist with a focus on memory management architectures for security.


  • Formal specification and verification
  • Compiler-based security hardening
  • Anti-malware techniques
  • Computer architecture
  • Operating systems and virtualization


  • MS, PhD, and Postdoc in Computer Science, 2012

    University of Illinois at Urbana-Champaign

  • BS in Computer Science, 2005

    University of Wisconsin-Eau Claire



Research Scientist

Intel Labs

Jun 2012 – Present Oregon
I define and evaluate innovative security architectures for mitigating exploits and malware. I draw on my expertise in architecture, compilers, operating systems, virtualization, HW/SW co-design, and formal methods to effectively devise solutions that are well-adapted to workload requirements.

PhD Student and Postdoc

University of Illinois at Urbana-Champaign

Sep 2005 – May 2012 Illinois

Advisor: Carl A. Gunter

National Defense Science and Engineering Graduate (NDSEG) Fellow

PhD Dissertation: Compact Integrity-Aware Architectures

MS Thesis: Dependable Emergency-Response Networking Based on Retaskable Network Infrastructures

TA for Advanced Computer Security (Instructor: Carl A. Gunter)

TA for Advanced Operating Systems (Instructor: Samuel T. King)


FPGA-Powered Candy Dispenser

Touchless dispensing with a photoresistor sensor and a PWM-controlled servo

Using Intel MPX to harden SafeStack

Configuring bounds registers and extending LLVM and Clang to instrument code to help prevent corruption of the safe stacks.

HTTP-controlled MIDI Alert Bell Connected Via Ethernet

Based on Contiki OS with the lightweight X86 protection domain support that I implemented.

Python X10 CM19A driver (unofficial)

Unofficial driver for the X10 CM19A remote control interface in Python, now maintained by Burns Fisher.

X86 Lightweight Protection Domain Support for Contiki

Memory management based on paging, software-switched segments, or hardware task switching.


(2012). Cumulative Attestation Kernels for Embedded Systems. IEEE Transactions on Smart Grid.


(2009). Sh@re: Negotiated audit in social networks. IEEE International Conference on Systems, Man and Cybernetics.



Issued patents:

  1. 10,642,752 (2020): Auxiliary processor resources
  2. 10,558,582 (2020): Technologies for execute only transactional memory
  3. 10,515,023 (2019): System for address mapping and translation protection
  4. 10,503,664 (2019): Virtual machine manager for address mapping and translation protection
  5. 10,453,114 (2019): Selective sharing of user information based on contextual relationship information, such as to crowd-source gifts of interest to a recipient
  6. 10,452,848 (2019): Memory scanning methods and apparatus
  7. 10,324,863 (2019): Protected memory view for nested page table access by virtual machine guests
  8. 10,318,733 (2019): Techniques for detecting malware with minimal performance degradation
  9. 10,235,301 (2019): Dynamic page table edit control
  10. 10,216,522 (2019): Technologies for indirect branch target security
  11. 10,157,277 (2018): Technologies for object-oriented memory management with extended segmentation
  12. 10,152,612 (2018): Cryptographic operations for secure page mapping in a virtual machine environment
  13. 10,104,122 (2018): Verified sensor data processing
  14. 10,061,918 (2018): System, apparatus and method for filtering memory access logging in a processor
  15. 10,007,784 (2018): Technologies for control flow exploit mitigation using processor trace
  16. 9,954,950 (2018): Attestable information flow control in computer systems
  17. 9,858,411 (2018): Execution profiling mechanism
  18. 9,830,162 (2017): Technologies for indirect branch target security
  19. 9,817,976 (2017): Techniques for detecting malware with minimal performance degradation
  20. 9,805,194 (2017): Memory scanning methods and apparatus
  21. 9,792,222 (2017): Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure
  22. 9,710,393 (2017): Dynamic page table edit control
  23. 9,703,703 (2017): Control of entry into protected memory views
  24. 9,665,373 (2017): Protecting confidential data with transactional processing in execute-only memory
  25. 9,501,637 (2016): Hardware shadow stack support for legacy guests
  26. 9,335,943 (2016): Method and apparatus for fine grain memory protection
  27. 9,124,635 (2015): Verified sensor data processing
  28. 8,458,791 (2013): Hardware-implemented hypervisor for root-of-trust monitoring and control of computer system
  29. 7,774,411 (2010): Secure electronic message transport protocol

Published patent applications:

  1. WO2020096639: Function as a Service (FaaS) System Enhancements
  2. 16/024,259: Protection of keys and sensitive data from attack within microprocessor architecture
  3. 16/024,257: Memory tagging for side-channel defense, memory safety, and sandboxing
  4. 16/024,547: Encoded inline capabilities
  5. 15/859,142: Apparatus and method for pausing processor trace for efficient analysis
  6. 15/721,082: Crypto-enforced capabilities for isolation
  7. 15/721,553: Installing and manipulating a secure virtual machine image through an untrusted hypervisor
  8. 15/713,573: Methods and arrangements to determine physical resource assignments
  9. 16/040,193: System, method and apparatus for automatic program compartmentalization
  10. 16/024,089: Techniques to provide function-level isolation with capability-based security
  11. 15/629,458: Hardened safe stack for return oriented programming attack mitigation
  12. 15/282,954: Enforcing memory operand types using protection keys
  13. 15/273,286: Access control
  14. 15/201,018: Regulating control transfers for execute-only code execution



App, kernel, and hypervisor development for Linux, Windows, and embedded systems with Boost and generics experience

X86 Assembly

Somewhat familar with assembly language for other architectures as well


Compiler framework


Bluespec SystemVerilog

High-Level Synthesis (HLS) language based on Term-Rewriting Systems


Model checker based on Term-Rewriting Systems and Linear-Temporal Logic


Interactive theorem prover



Experience using Intel Quartus and Xilinx Vivado FPGA toolchains. Experience using Synopsys VCS and Mentor Graphics Modelsim simulators. Experience extending and maintaining an in-house Verilog simulator during an internship with Cray, Inc.


Logic programming language

Professional Service and Volunteering

Professional society memberships:

  • Association for Computing Machinery (ACM)
  • IEEE

PC member:

  • TRUST 2010 & 2011

Journal reviews:

  • 2019 IEEE Transactions on Networking
  • 2013 IEEE Transactions on Information Forensics & Security (TIFS)
  • 2009 Journal of Computer Security (JCS)
  • 2009 IEEE Transactions on Industrial Electronics (TIE)
  • 2007 ACM Transactions on the Web (TWEB)
  • 2005 ACM Transactions on Information and System Security (TISSEC)

Conference and workshop reviews:

  • 2013 IEEE PowerTech
  • 2009 International Conference on Distributed Computing Systems (ICDCS)
  • 2009 IEEE Symposium on Security and Privacy (Oakland)
  • 2008 IEEE Workshop on Policies for Distributed Systems and Networks (POLICY)
  • 2008 Hawaiian International Conference on System Sciences (HICSS)
  • 2007 IEEE Computer Security Foundations Symposium (CSF)
  • 2007 ACM Workshop on Privacy in the Electronic Society (WPES)
  • 2006 IEEE International Conference on Network Protocols (ICNP)
  • 2006 IFIP International Conference on Critical Infrastructure Protection (ICCIP)
  • 2006 ACM Workshop on Privacy in the Electronic Society (WPES)




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