Michael LeMay

Michael LeMay

Senior Staff Research Scientist

Intel Labs

Biography

Research Scientist with a focus on memory management architectures for security.

Interests
  • Formal specification and verification
  • Compiler-based security hardening
  • Anti-malware techniques
  • Computer architecture
  • Operating systems and virtualization
Education
  • MS, PhD, and Postdoc in Computer Science, 2012

    University of Illinois at Urbana-Champaign

  • BS in Computer Science, 2005

    University of Wisconsin-Eau Claire

Experience

 
 
 
 
 
Senior Staff Research Scientist
Jun 2012 – Present Oregon

I define and evaluate innovative security architectures for mitigating exploits and malware. I draw on my expertise in architecture, compilers, operating systems, virtualization, HW/SW co-design, and formal methods to effectively devise solutions that are well-adapted to workload requirements.

Co-lead liaison from Intel for the SRC JUMP CONIX research center.

 
 
 
 
 
PhD Student and Postdoc
Sep 2005 – May 2012 Illinois

Advisor: Carl A. Gunter

National Defense Science and Engineering Graduate (NDSEG) Fellow

PhD Dissertation: Compact Integrity-Aware Architectures

MS Thesis: Dependable Emergency-Response Networking Based on Retaskable Network Infrastructures

TA for Advanced Computer Security (Instructor: Carl A. Gunter)

TA for Advanced Operating Systems (Instructor: Samuel T. King)

Other Publications

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(2021). Isolation Without Taxation: Near Zero Cost Transitions for SFI. Foundations of Computer Security (FCS).

PDF Project

(2014). Power-Based Diagnosis of Node Silence in Remote High-End Sensing Systems. ACM Transactions on Sensor Networks (ToSN).

PDF DOI

(2014). Protecting Sensor Data from Malware Attacks (pages 178-197). Intel Technology Journal (ITJ).

PDF

(2011). Reliable telemetry in white spaces using remote attestation. Annual Computer Security Applications Conference (ACSAC).

PDF Slides DOI

(2010). Diagnostic Powertracing for Sensor Node Failure Analysis. Information Processing in Sensor Networks (IPSN).

PDF DOI

(2009). Sh@re: Negotiated audit in social networks. Systems, Man and Cybernetics (SMC).

PDF DOI

(2009). Cumulative Attestation Kernels for Embedded Systems. European Symposium on Research in Computer Security (ESORICS).

PDF Slides DOI

(2009). Collaborative Recommender Systems for Building Automation. Hawaii International Conference on System Sciences (HICSS).

PDF Slides DOI

(2007). Supporting Emergency-Response by Retasking Network Infrastructures. HotNets.

PDF Slides

(2007). PolicyMorph: interactive policy transformations for a logical attribute-based access control framework. Symposium on Access Control Models and Technologies (SACMAT).

PDF Slides DOI

(2007). Unified Architecture for Large-Scale Attested Metering. Hawaii International Conference on System Sciences (HICSS).

PDF Slides DOI

(2006). Acoustic Surveillance of Physically Unmodified PCs. Security and Management (SAM).

PDF Slides

(2004). Comprehensive message control and assurance with the secure email transport protocol. Electro/Information Technology (EIT).

DOI

(2004). Abstracting Low-Level Network Programming With ACE, a Pattern-Oriented Network Programming Framework. Software Engineering Research and Practice (SERP).

PDF

Patents

Issued patents:

  1. 11,436,161 (2022): System for address mapping and translation protection
  2. 11,429,580 (2022): Collision-free hashing for accessing cryptographic computing metadata and for cache expansion
  3. 11,416,624 (2022): Cryptographic computing using encrypted base addresses and used in multi-tenant environments
  4. 11,416,414 (2022): Technologies for execute only transactional memory
  5. 11,409,662 (2022): Apparatus and method for efficient process-based compartmentalization
  6. 11,403,234 (2022): Cryptographic computing using encrypted base addresses and used in multi-tenant environments
  7. 11,392,492 (2022): Memory management apparatus and method for compartmentalization using linear address metadata
  8. 11,360,876 (2022): Apparatus and method for pausing processor trace for efficient analysis
  9. 11,354,423 (2022): Cryptographic isolation of memory compartments in a computing environment
  10. 11,321,469 (2022): Microprocessor pipeline circuitry to support cryptographic computing
  11. 11,250,165 (2022): Binding of cryptographic operations to context or speculative execution restrictions
  12. 11,222,127 (2022): Processor hardware and instructions for SHA3 cryptographic operations
  13. 11,216,366 (2022): Security check systems and methods for memory allocations
  14. 11,188,639 (2021): System, method and apparatus for automatic program compartmentalization
  15. 11,171,983 (2021): Techniques to provide function-level isolation with capability-based security
  16. 11,163,569 (2021): Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety
  17. 11,144,479 (2021): System for address mapping and translation protection
  18. 11,080,401 (2021): Memory scanning methods and apparatus
  19. 11,036,850 (2021): Technologies for object-oriented memory management with extended segmentation
  20. 11,030,113 (2021): Apparatus and method for efficient process-based compartmentalization
  21. 10,884,952 (2021): Enforcing memory operand types using protection keys
  22. 10,860,709 (2020): Encoded inline capabilities
  23. 10,795,997 (2020): Hardened safe stack for return oriented programming attack mitigation
  24. 10,785,028 (2020): Protection of keys and sensitive data from attack within microprocessor architecture
  25. 10,769,272 (2020): Technology to protect virtual machines from malicious virtual machine managers
  26. 10,706,164 (2020): Crypto-enforced capabilities for isolation
  27. 10,642,752 (2020): Auxiliary processor resources
  28. 10,558,582 (2020): Technologies for execute only transactional memory
  29. 10,515,023 (2019): System for address mapping and translation protection
  30. 10,503,664 (2019): Virtual machine manager for address mapping and translation protection
  31. 10,453,114 (2019): Selective sharing of user information based on contextual relationship information, such as to crowd-source gifts of interest to a recipient
  32. 10,452,848 (2019): Memory scanning methods and apparatus
  33. 10,324,863 (2019): Protected memory view for nested page table access by virtual machine guests
  34. 10,318,733 (2019): Techniques for detecting malware with minimal performance degradation
  35. 10,235,301 (2019): Dynamic page table edit control
  36. 10,216,522 (2019): Technologies for indirect branch target security
  37. 10,157,277 (2018): Technologies for object-oriented memory management with extended segmentation
  38. 10,152,612 (2018): Cryptographic operations for secure page mapping in a virtual machine environment
  39. 10,104,122 (2018): Verified sensor data processing
  40. 10,061,918 (2018): System, apparatus and method for filtering memory access logging in a processor
  41. 10,007,784 (2018): Technologies for control flow exploit mitigation using processor trace
  42. 9,954,950 (2018): Attestable information flow control in computer systems
  43. 9,858,411 (2018): Execution profiling mechanism
  44. 9,830,162 (2017): Technologies for indirect branch target security
  45. 9,817,976 (2017): Techniques for detecting malware with minimal performance degradation
  46. 9,805,194 (2017): Memory scanning methods and apparatus
  47. 9,792,222 (2017): Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure
  48. 9,710,393 (2017): Dynamic page table edit control
  49. 9,703,703 (2017): Control of entry into protected memory views
  50. 9,665,373 (2017): Protecting confidential data with transactional processing in execute-only memory
  51. 9,501,637 (2016): Hardware shadow stack support for legacy guests
  52. 9,335,943 (2016): Method and apparatus for fine grain memory protection
  53. 9,124,635 (2015): Verified sensor data processing
  54. 8,458,791 (2013): Hardware-implemented hypervisor for root-of-trust monitoring and control of computer system
  55. 7,774,411 (2010): Secure electronic message transport protocol

Published patent applications:

  1. 17/357,963: REGION-BASED DETERMINISTIC MEMORY SAFETY

  2. 17/704,771: TAGLESS IMPLICIT INTEGRITY WITH MULTI-PERSPECTIVE PATTERN SEARCH

  3. 17/696,330: RATCHET POINTERS TO ENFORCE BYTE-GRANULAR BOUNDS CHECKS ON MULTIPLE VIEWS OF AN OBJECT

  4. 17/699,593: CRYPTOGRAPHIC DATA OBJECTS PAGE CONVERSION

  5. 17/696,153: CRYPTOGRAPHIC ENFORCEMENT OF BORROW CHECKING

  6. 17/692,464: COMPARTMENT ISOLATION FOR LOAD STORE FORWARDING

  7. 17/693,748: GENERATING ENCRYPTED CAPABILITIES WITHIN BOUNDS

  8. 17/682,997: COMPILER-DIRECTED SELECTION OF OBJECTS FOR CAPABILITY PROTECTION

  9. 17/561,828: PROCESS OBJECT RE-KEYING DURING PROCESS CREATION IN CRYPTOGRAPHIC COMPUTING

  10. 17/485,213: OBJECT AND CACHELINE GRANULARITY CRYPTOGRAPHIC MEMORY INTEGRITY

  11. 17/559,385: DATA OBLIVIOUS CRYPTOGRAPHIC COMPUTING

  12. 17/561,817: TYPED STORE BUFFERS FOR HARDENING STORE FORWARDING

  13. 17/485,213: OBJECT AND CACHELINE GRANULARITY CRYPTOGRAPHIC MEMORY INTEGRITY

  14. 17/314,349: TECHNOLOGY TO CONTROL SYSTEM CALL INVOCATIONS WITHIN A SINGLE ADDRESS SPACE

  15. 17/255,588: FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS

  16. 16/998,913: PROTECTION OF KEYS AND SENSITIVE DATA FROM ATTACK WITHIN MICROPROCESSOR ARCHITECTURE

  17. 16/862,022: MEMORY WRITE FOR OWNERSHIP ACCESS IN A CORE

  18. 16/776,467: CRYPTOGRAPHIC COMPUTING ENGINE FOR MEMORY LOAD AND STORE UNITS OF A MICROARCHITECTURE PIPELINE

  19. 16/740,359: CRYPTOGRAPHIC COMPUTING USING ENCRYPTED BASE ADDRESSES AND USED IN MULTI-TENANT ENVIRONMENTS

  20. 16/724,026: DATA ENCRYPTION BASED ON IMMUTABLE POINTERS

  21. 16/722,342: POINTER BASED DATA ENCRYPTION

  22. WO2020096639: Function as a Service (FaaS) System Enhancements

  23. 16/024,257: Memory tagging for side-channel defense, memory safety, and sandboxing

  24. 15/721,553: Installing and manipulating a secure virtual machine image through an untrusted hypervisor

  25. 15/713,573: Methods and arrangements to determine physical resource assignments

  26. 16/040,193: System, method and apparatus for automatic program compartmentalization

  27. 15/273,286: Access control

  28. 15/201,018: Regulating control transfers for execute-only code execution

Skills

C/C++

App, kernel, and hypervisor development for Linux, Windows, and embedded systems with Boost and generics experience

Rust
Go
SMT-LIB / Z3

SAT/SMT solver (completed Coursera course)

X86 Assembly

Somewhat familiar with assembly language for other architectures as well

LLVM/Clang

Compiler framework

Bluespec SystemVerilog

High-Level Synthesis (HLS) language based on Term-Rewriting Systems

Maude

Model checker based on Term-Rewriting Systems and Linear-Temporal Logic

Isabelle/HOL

Interactive theorem prover

Python
Java
Verilog/VHDL

Experience using Intel Quartus and Xilinx Vivado FPGA toolchains. Experience using Synopsys VCS and Mentor Graphics Modelsim simulators. Experience extending and maintaining an in-house Verilog simulator during an internship with Cray, Inc.

Prolog

Logic programming language

Professional Service and Volunteering

Professional society memberships:

  • Senior Member of the Association for Computing Machinery (ACM)
  • Senior Member of IEEE

PC member:

  • TRUST 2010 & 2011

Journal reviews:

  • 2019 IEEE Transactions on Networking
  • 2013 IEEE Transactions on Information Forensics & Security (TIFS)
  • 2009 Journal of Computer Security (JCS)
  • 2009 IEEE Transactions on Industrial Electronics (TIE)
  • 2007 ACM Transactions on the Web (TWEB)
  • 2005 ACM Transactions on Information and System Security (TISSEC)

Conference and workshop reviews:

  • 2021 Design Automation Conference (DAC)
  • 2013 IEEE PowerTech
  • 2009 International Conference on Distributed Computing Systems (ICDCS)
  • 2009 IEEE Symposium on Security and Privacy (Oakland)
  • 2008 IEEE Workshop on Policies for Distributed Systems and Networks (POLICY)
  • 2008 Hawaiian International Conference on System Sciences (HICSS)
  • 2007 IEEE Computer Security Foundations Symposium (CSF)
  • 2007 ACM Workshop on Privacy in the Electronic Society (WPES)
  • 2006 IEEE International Conference on Network Protocols (ICNP)
  • 2006 IFIP International Conference on Critical Infrastructure Protection (ICCIP)
  • 2006 ACM Workshop on Privacy in the Electronic Society (WPES)

Selected Mentoring Experiences:

Volunteering:

Hobbies

Contact

For messages related to my work at Intel, please contact me at michael dot lemay at intel dot com.

For other messages, please contact me at m at lemays dot org.