Michael LeMay

Michael LeMay

Senior Staff Research Scientist

Intel Labs

Biography

Research Scientist with a focus on memory management architectures for security.

Interests
  • Formal specification and verification
  • Compiler-based security hardening
  • Anti-malware techniques
  • Computer architecture
  • Operating systems and virtualization
Education
  • MS, PhD, and Postdoc in Computer Science, 2012

    University of Illinois at Urbana-Champaign

  • BS in Computer Science, 2005

    University of Wisconsin-Eau Claire

Experience

 
 
 
 
 
Senior Staff Research Scientist
Jun 2012 – Present Oregon
I define and evaluate innovative security architectures for mitigating exploits and malware. I draw on my expertise in architecture, compilers, operating systems, virtualization, HW/SW co-design, and formal methods to effectively devise solutions that are well-adapted to workload requirements.
 
 
 
 
 
PhD Student and Postdoc
Sep 2005 – May 2012 Illinois

Advisor: Carl A. Gunter

National Defense Science and Engineering Graduate (NDSEG) Fellow

PhD Dissertation: Compact Integrity-Aware Architectures

MS Thesis: Dependable Emergency-Response Networking Based on Retaskable Network Infrastructures

TA for Advanced Computer Security (Instructor: Carl A. Gunter)

TA for Advanced Operating Systems (Instructor: Samuel T. King)

Recent Publications

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(2014). Power-Based Diagnosis of Node Silence in Remote High-End Sensing Systems. ACM Transactions on Sensor Networks.

PDF DOI

(2014). Protecting Sensor Data from Malware Attacks (pages 178-197). Intel Technology Journal.

PDF

(2011). Reliable telemetry in white spaces using remote attestation. ACSAC.

PDF Slides DOI

(2010). Diagnostic Powertracing for Sensor Node Failure Analysis. IPSN.

PDF DOI

(2009). Sh@re: Negotiated audit in social networks. IEEE International Conference on Systems, Man and Cybernetics.

PDF DOI

(2009). Cumulative Attestation Kernels for Embedded Systems. ESORICS.

PDF Slides DOI

(2009). Collaborative Recommender Systems for Building Automation. HICSS.

PDF Slides DOI

(2007). Unified Architecture for Large-Scale Attested Metering. HICSS.

PDF Slides DOI

Patents

Issued patents:

  1. 11,080,401 (2021): Memory scanning methods and apparatus
  2. 11,036,850 (2021): Technologies for object-oriented memory management with extended segmentation
  3. 11,030,113 (2021): Apparatus and method for efficient process-based compartmentalization
  4. 10,884,952 (2021): Enforcing memory operand types using protection keys
  5. 10,860,709 (2020): Encoded inline capabilities
  6. 10,795,997 (2020): Hardened safe stack for return oriented programming attack mitigation
  7. 10,785,028 (2020): Protection of keys and sensitive data from attack within microprocessor architecture
  8. 10,769,272 (2020): Technology to protect virtual machines from malicious virtual machine managers
  9. 10,706,164 (2020): Crypto-enforced capabilities for isolation
  10. 10,642,752 (2020): Auxiliary processor resources
  11. 10,558,582 (2020): Technologies for execute only transactional memory
  12. 10,515,023 (2019): System for address mapping and translation protection
  13. 10,503,664 (2019): Virtual machine manager for address mapping and translation protection
  14. 10,453,114 (2019): Selective sharing of user information based on contextual relationship information, such as to crowd-source gifts of interest to a recipient
  15. 10,452,848 (2019): Memory scanning methods and apparatus
  16. 10,324,863 (2019): Protected memory view for nested page table access by virtual machine guests
  17. 10,318,733 (2019): Techniques for detecting malware with minimal performance degradation
  18. 10,235,301 (2019): Dynamic page table edit control
  19. 10,216,522 (2019): Technologies for indirect branch target security
  20. 10,157,277 (2018): Technologies for object-oriented memory management with extended segmentation
  21. 10,152,612 (2018): Cryptographic operations for secure page mapping in a virtual machine environment
  22. 10,104,122 (2018): Verified sensor data processing
  23. 10,061,918 (2018): System, apparatus and method for filtering memory access logging in a processor
  24. 10,007,784 (2018): Technologies for control flow exploit mitigation using processor trace
  25. 9,954,950 (2018): Attestable information flow control in computer systems
  26. 9,858,411 (2018): Execution profiling mechanism
  27. 9,830,162 (2017): Technologies for indirect branch target security
  28. 9,817,976 (2017): Techniques for detecting malware with minimal performance degradation
  29. 9,805,194 (2017): Memory scanning methods and apparatus
  30. 9,792,222 (2017): Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure
  31. 9,710,393 (2017): Dynamic page table edit control
  32. 9,703,703 (2017): Control of entry into protected memory views
  33. 9,665,373 (2017): Protecting confidential data with transactional processing in execute-only memory
  34. 9,501,637 (2016): Hardware shadow stack support for legacy guests
  35. 9,335,943 (2016): Method and apparatus for fine grain memory protection
  36. 9,124,635 (2015): Verified sensor data processing
  37. 8,458,791 (2013): Hardware-implemented hypervisor for root-of-trust monitoring and control of computer system
  38. 7,774,411 (2010): Secure electronic message transport protocol

Published patent applications:

  1. 17/314,349: TECHNOLOGY TO CONTROL SYSTEM CALL INVOCATIONS WITHIN A SINGLE ADDRESS SPACE
  2. 17/255,588: FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS
  3. 16/998,913: PROTECTION OF KEYS AND SENSITIVE DATA FROM ATTACK WITHIN MICROPROCESSOR ARCHITECTURE
  4. 16/998,912: SECURITY CHECK SYSTEMS AND METHODS FOR MEMORY ALLOCATIONS
  5. 16/862,022: MEMORY WRITE FOR OWNERSHIP ACCESS IN A CORE
  6. 16/776,467: CRYPTOGRAPHIC COMPUTING ENGINE FOR MEMORY LOAD AND STORE UNITS OF A MICROARCHITECTURE PIPELINE
  7. 16/740,359: CRYPTOGRAPHIC COMPUTING USING ENCRYPTED BASE ADDRESSES AND USED IN MULTI-TENANT ENVIRONMENTS
  8. 16/724,105: MICROPROCESSOR PIPELINE CIRCUITRY TO SUPPORT CRYPTOGRAPHIC COMPUTING
  9. 16/724,026: DATA ENCRYPTION BASED ON IMMUTABLE POINTERS
  10. 16/723,977: CRYPTOGRAPHIC ISOLATION OF MEMORY COMPARTMENTS IN A COMPUTING ENVIRONMENT
  11. 16/723,468: BINDING OF CRYPTOGRAPHIC OPERATIONS TO CONTEXT OR SPECULATIVE EXECUTION RESTRICTIONS
  12. 16/722,707: CRYPTOGRAPHIC COMPUTING USING ENCRYPTED BASE ADDRESSES AND USED IN MULTI-TENANT ENVIRONMENTS
  13. 16/722,342: POINTER BASED DATA ENCRYPTION
  14. 16/709,837: PROCESSOR HARDWARE AND INSTRUCTIONS FOR SHA3 CRYPTOGRAPHIC OPERATIONS
  15. WO2020096639: Function as a Service (FaaS) System Enhancements
  16. 16/024,257: Memory tagging for side-channel defense, memory safety, and sandboxing
  17. 15/859,142: Apparatus and method for pausing processor trace for efficient analysis
  18. 15/721,553: Installing and manipulating a secure virtual machine image through an untrusted hypervisor
  19. 15/713,573: Methods and arrangements to determine physical resource assignments
  20. 16/040,193: System, method and apparatus for automatic program compartmentalization
  21. 16/024,089: Techniques to provide function-level isolation with capability-based security
  22. 15/273,286: Access control
  23. 15/201,018: Regulating control transfers for execute-only code execution

Skills

C/C++

App, kernel, and hypervisor development for Linux, Windows, and embedded systems with Boost and generics experience

Rust
Go
SMT-LIB / Z3

SAT/SMT solver (completed Coursera course)

X86 Assembly

Somewhat familiar with assembly language for other architectures as well

LLVM/Clang

Compiler framework

Bluespec SystemVerilog

High-Level Synthesis (HLS) language based on Term-Rewriting Systems

Maude

Model checker based on Term-Rewriting Systems and Linear-Temporal Logic

Isabelle/HOL

Interactive theorem prover

Python
Verilog/VHDL

Experience using Intel Quartus and Xilinx Vivado FPGA toolchains. Experience using Synopsys VCS and Mentor Graphics Modelsim simulators. Experience extending and maintaining an in-house Verilog simulator during an internship with Cray, Inc.

Prolog

Logic programming language

Professional Service and Volunteering

Professional society memberships:

  • Association for Computing Machinery (ACM)
  • IEEE

PC member:

  • TRUST 2010 & 2011

Journal reviews:

  • 2019 IEEE Transactions on Networking
  • 2013 IEEE Transactions on Information Forensics & Security (TIFS)
  • 2009 Journal of Computer Security (JCS)
  • 2009 IEEE Transactions on Industrial Electronics (TIE)
  • 2007 ACM Transactions on the Web (TWEB)
  • 2005 ACM Transactions on Information and System Security (TISSEC)

Conference and workshop reviews:

  • 2021 Design Automation Conference (DAC)
  • 2013 IEEE PowerTech
  • 2009 International Conference on Distributed Computing Systems (ICDCS)
  • 2009 IEEE Symposium on Security and Privacy (Oakland)
  • 2008 IEEE Workshop on Policies for Distributed Systems and Networks (POLICY)
  • 2008 Hawaiian International Conference on System Sciences (HICSS)
  • 2007 IEEE Computer Security Foundations Symposium (CSF)
  • 2007 ACM Workshop on Privacy in the Electronic Society (WPES)
  • 2006 IEEE International Conference on Network Protocols (ICNP)
  • 2006 IFIP International Conference on Critical Infrastructure Protection (ICCIP)
  • 2006 ACM Workshop on Privacy in the Electronic Society (WPES)

Volunteering:

Hobbies

Contact