Intel

Principal Engineer, Oregon (June 2012–present)

I am an architect for x86 Memory Tagging Technology (formerly known as ChkTag):

As part of that role, I participate in the x86 Ecosystem Advisory Group:

My research has generated or influenced hardware and software security architectures deployed on a large proportion of computer systems in use today.

I have contributed to shipping processor security technologies, including Control-Flow Enforcement Technology (CET) and VT-Redirect Protection (VT-rp). Such technologies are important for mitigating AI-generated exploits.

I designed and co-developed deterministic spatial safety support for MiraclePtr in the Chrome browser.

My LLVM-based research on shielding stack memory from corruption helped lead to a 2022 paper in a top-tier programming languages conference covered by ZDNet.

I also researched approaches for scalable isolation, for example using segmentation to accelerate WebAssembly (upstreamed in wasm2c).

Education

M.S. & Ph.D. in Computer Science

University of Illinois at Urbana-Champaign, August 2011.

Ph.D. dissertation: Compact Integrity-Aware Architectures. Committee:

Postdoc through May 2012.

B.S. in Computer Science

University of Wisconsin-Eau Claire, May 2005.

UWEC Outstanding CS Senior of the Year, 2005. Karlgaard Scholarship. Summa cum laude. National Merit Scholarship Finalist.

Skills

  • C++

  • C

  • x86 assembly language

  • Python

  • Rust

  • LLVM/Clang

  • SMT-LIB / Z3 (completed Coursera course)

Awards

Mentoring

Volunteering

Favorite resources