Research Scientist with a focus on memory management architectures for security.
MS, PhD, and Postdoc in Computer Science, 2012
University of Illinois at Urbana-Champaign
BS in Computer Science, 2005
University of Wisconsin-Eau Claire
My research has generated or influenced hardware and software security architectures deployed on a large proportion of computer systems in use today.
I have contributed to shipping processor security technologies, including Control-Flow Enforcement Technology (CET) and VT-Redirect Protection (VT-rp).
Principal Investigator for Intel’s project on Cryptographic Capability Computing (C3) in the DARPA HARDEN program.
I designed and co-developed deterministic spatial safety support for MiraclePtr in the Chrome browser.
My LLVM-based research on shielding stack memory from corruption helped lead to a 2022 paper in a top-tier programming languages conference covered by ZDNet.
I also researched approaches for scalable isolation, e.g., using segmentation to accelerate WebAssembly (upstreamed in wasm2c).
Advisor: Carl A. Gunter
National Defense Science and Engineering Graduate (NDSEG) Fellow
PhD Dissertation: Compact Integrity-Aware Architectures
MS Thesis: Dependable Emergency-Response Networking Based on Retaskable Network Infrastructures
TA for Advanced Computer Security (Instructor: Carl A. Gunter)
TA for Advanced Operating Systems (Instructor: Samuel T. King)
Issued patents:
Published patent applications:
App, kernel, and hypervisor development for Linux, Windows, and embedded systems with Boost and generics experience
Including CMake
(e.g., Bash)
Including for WebAssembly
SAT/SMT solver (completed Coursera course)
Somewhat familiar with assembly language for other architectures as well
Compiler framework
High-Level Synthesis (HLS) language based on Term-Rewriting Systems
Model checker based on Term-Rewriting Systems and Linear-Temporal Logic
Interactive theorem prover
Experience using Intel Quartus and Xilinx Vivado FPGA toolchains. Experience using Synopsys VCS and Mentor Graphics Modelsim simulators. Experience extending and maintaining an in-house Verilog simulator during an internship with Cray, Inc.
Logic programming language
Professional society memberships:
Program Committee (PC) member:
Journal reviews:
Conference and workshop reviews:
Selected Mentoring Experiences:
Volunteering:
For messages related to my work at Intel, please contact me at michael dot lemay at intel dot com.
For other messages, please contact me at m at lemays dot org.
I post a mix of professional content and personal content on my website, and I categorize my posts accordingly. Separate RSS/Atom feeds are generated for each of those categories, and there is also a combined feed: